In modern consumer devices, such as cellular or connectivity applications, synthesizer circuits are implemented for generating one or more signals having a desired output frequency. Due to the advantages of digital implementation, like low power consumption, testability, small required chip area and the like, synthesizer circuits can be preferably realized in the digital domain.
In general, the digital synthesizer circuits may comprise a digital phase-locked loop (DPLL) for controlling an oscillator, like a digitally controlled oscillator (DCO). More particularly, the output signal of the DCO can be controlled such that it maintains a desired relationship with an input reference signal. In particular, a desired frequency and/or phase relationship may be maintained. The output signal of the DCO is fed back to a timing comparator via a feedback frequency divider. The timing comparator is arranged to compare the timing of the reference signal supplied with that of the frequency divided DCO output signal. The timing comparator may be a phase detector for example, which may be implemented as a time-to-digital converter (TDC). The result of the timing comparison is used to adjust the DCO output frequency via a loop filter. Thus, a desired frequency and/or phase relationship between the reference signal and the output signal of the DCO can be maintained.
The frequency divider may be a fractional divider, which supports non-integer division ratios as well as integer division ratios. In this case the DPLL may comprise a delta sigma (ΔΣ) modulator which receives a desired division ratio, which may be a rational number. This division ratio may be used to define to the desired output frequency. The delta sigma modulator generates a sequence of integers based on the desired divide ratio, so that the average of the integers equals the divide ratio. The integers from the sequence are used to control the actual division ratio of the frequency divider in a time dependent way according to the sequence. As a result, the DPLL will output a signal having an average frequency corresponding to the desired division ratio. However, while the average frequency output may be correct, phase errors may be introduced into the VCO/DCO output signal when the actual division ratio is not continuously equal to the desired division ratio. Thus the divider acts as a timing modulator that imparts jitter to the timing of the oscillator signal.
US 2005/0285685 A1 discloses a fractional-N phase locked loop having a first delta sigma modulator which is supplied with a divide value and which generates a divide control signal. The first delta sigma modulator integrates an error term indicative of a difference between a value of the generated divide control signal and the divide value supplied to the first delta sigma modulator. A phase error cancellation signal is generated by quantizing the integrated error term using a second delta sigma modulator. In one embodiment the error term is used in the second delta sigma modulator in the process of quantizing the integrated error term, thereby limiting the low pass filter effects of the second delta sigma modulator in the cancellation signal.
US 2005/0094757 A1 discloses methods and modules for reducing the phase noise generated in a fractional-N frequency synthesizer. In particular, it seeks to provide improved matching between a cancellation signal and a phase error signal. The methods are based on swapping phase signals to achieve the same average delay for each phase signal path, compensation and resynchronization of phase signals, and shuffling of digital-to analogue unit elements used to produce specific quantization levels. One method is based on digital gain compensation used to correct for frequency-dependent error arising from 25 differences between horizontal slicing quantization techniques and conventional vertical slicing techniques. It employs a combined phase detector and digital-to-analogue converter module.
However, the TDC 2 resolution may vary during processing of the consumer device due to process, temperature and voltage variations. Thus, the determined or measured phase jitter of the output signal of the DCO is inaccurate resulting in an inaccurate output signal of the DCO.
When phase cancellation is performed for example, it is desirable that the proportionality between timing differences and the resulting output signal values of the TDC matches the proportionality between predicted phase differences and the resulting prediction signal. If these two relations do not match, error cancellation will not be perfect. Similarly, when the TDC output is used as an absolute time or phase measurement, deviations between the ideally intended proportionality and the actual proportionality between timing differences and the resulting TDC output signal values lead to errors. Therefore it is desirable to provide at least for relative calibration of the proportion
It is an object to provide for an improved fractional-N phase locked loops. Alternatively, or in addition, it is an object of to provide an improved module for calibrating and/or normalizing a timing comparator.